Intermediate
30 min
0

Provide a stable frequency reference for various electronic systems with Si5351A and ATmega32

Sync, Lock, and Rock

Clock Gen Click with EasyAVR v7

Published Nov 01, 2023

Click board™

Clock Gen Click

Development board

EasyAVR v7

Compiler

NECTO Studio

MCU

ATmega32

Experience unmatched timing precision by integrating a reliable clock generator into your solution

A

A

Hardware Overview

How does it work?

Clock Gen Click is based on the Si5351A, a versatile I2C programmable clock generator ideally suited for replacing crystals, crystal oscillators, VCXOs, PLLs, and buffers. The Si5351A consists of an input, two syntheses, and an output stage. The input stage accepts an external crystal (XTAL on XA and XB pins). The first stage of synthesis multiplies the input frequencies to a high-frequency intermediate clock, while the second stage of synthesis uses high-resolution MultiSynth fractional dividers to generate the desired output frequencies. Additional integer division is provided at the output stage for generating output frequencies as low as 2.5 kHz. Crosspoint switches at each synthesis stage allow total flexibility in routing any of the inputs to any of the outputs. Because of this high resolution and flexible synthesis architecture, the Si5351A can generate synchronous or free-running non-integer related clock frequencies at each output, enabling one device to synthesize clocks for multiple clock domains in a design. The Si5351A uses a fixed-frequency standard AT-cut crystal to reference the internal oscillator. The oscillator's output can

provide a free-running reference to one or both PLLs for generating asynchronous clocks. The oscillator's output frequency operates at the crystal frequency of 25 MHz. Internal load capacitors are provided to eliminate the need for external components when connecting a crystal to the Si5351A. The total internal XTAL load capacitance (CL) can be selected as 0, 6, 8, or 10 pF. The Si5351A uses two stages of synthesis to generate its final output clocks. The first stage uses PLLs to multiply the lower-frequency input references to a high-frequency intermediate clock. The second stage uses high-resolution MultiSynth fractional dividers to generate the required output frequencies. Only two unique frequencies above 112.5 MHz can be simultaneously output. For example, 125 MHz (CLK0), 130 MHz (CLK1), and 150 MHz (CLK2) are not allowed. Both PLLs are locked to the same source (XTAL). The crosspoint switch at the input of the second stage allows any of the MultiSynth dividers to connect to PLLA or PLLB. This flexible synthesis architecture allows any of the outputs to generate synchronous or non-synchronous clocks, with spread spectrum or

without spread spectrum, and with the flexibility of generating non-integer-related clock frequencies at each output. Frequencies down to 2.5 kHz can be generated by applying the R divider at the output of the Multisynth. All output drivers generate CMOS level outputs with a single output voltage supply pin (VDDO), allowing a different voltage signal level (1.8, 2.5, or 3.3 V) at the output banks. The output voltage level selection can be chosen by moving an SMD jumper labeled VDDO SEL to an appropriate position (3V3 or EXT). If 3V3 is chosen, the VDDO is supplied by the board. Otherwise, an external supply must be connected to the voltage level supply pin. This Click board™ uses the I2C communication interface and can be operated only with a 3.3V logic voltage level. The board must perform appropriate logic voltage level conversion before using MCUs with different logic levels. Also, it comes equipped with a library containing functions and an example code that can be used, as a reference, for further development.

Clock Gen Click top side image
Clock Gen Click bottom side image

Features overview

Development board

EasyAVR v7 is the seventh generation of AVR development boards specially designed for the needs of rapid development of embedded applications. It supports a wide range of 16-bit AVR microcontrollers from Microchip and has a broad set of unique functions, such as a powerful onboard mikroProg programmer and In-Circuit debugger over USB. The development board is well organized and designed so that the end-user has all the necessary elements in one place, such as switches, buttons, indicators, connectors, and others. With four different connectors for each port, EasyAVR v7 allows you to connect accessory boards, sensors, and custom electronics more

efficiently than ever. Each part of the EasyAVR v7 development board contains the components necessary for the most efficient operation of the same board. An integrated mikroProg, a fast USB 2.0 programmer with mikroICD hardware In-Circuit Debugger, offers many valuable programming/debugging options and seamless integration with the Mikroe software environment. Besides it also includes a clean and regulated power supply block for the development board. It can use a wide range of external power sources, including an external 12V power supply, 7-12V AC or 9-15V DC via DC connector/screw terminals, and a power source via the USB Type-B (USB-B)

connector. Communication options such as USB-UART and RS-232 are also included, alongside the well-established mikroBUS™ standard, three display options (7-segment, graphical, and character-based LCD), and several different DIP sockets which cover a wide range of 16-bit AVR MCUs. EasyAVR v7 is an integral part of the Mikroe ecosystem for rapid development. Natively supported by Mikroe software tools, it covers many aspects of prototyping and development thanks to a considerable number of different Click boards™ (over a thousand boards), the number of which is growing every day.

EasyAVR v7 horizontal image

Microcontroller Overview

MCU Card / MCU

default

Architecture

AVR

MCU Memory (KB)

32

Silicon Vendor

Microchip

Pin count

40

RAM (Bytes)

2048

Used MCU Pins

mikroBUS™ mapper

NC
NC
AN
NC
NC
RST
NC
NC
CS
NC
NC
SCK
NC
NC
MISO
NC
NC
MOSI
Power Supply
3.3V
3.3V
Ground
GND
GND
NC
NC
PWM
NC
NC
INT
NC
NC
TX
NC
NC
RX
I2C Clock
PC0
SCL
I2C Data
PC1
SDA
NC
NC
5V
Ground
GND
GND
1

Take a closer look

Schematic

Clock Gen Click Schematic schematic

Step by step

Project assembly

EasyAVR v7 front image hardware assembly

Start by selecting your development board and Click board™. Begin with the EasyAVR v7 as your development board.

EasyAVR v7 front image hardware assembly
GNSS2 Click front image hardware assembly
MCU DIP 40 hardware assembly
GNSS2 Click complete accessories setup image hardware assembly
EasyAVR v7 Access DIP MB 1 - upright/background hardware assembly
Necto image step 2 hardware assembly
Necto image step 3 hardware assembly
Necto image step 4 hardware assembly
NECTO Compiler Selection Step Image hardware assembly
NECTO Output Selection Step Image hardware assembly
Necto image step 6 hardware assembly
Necto DIP image step 7 hardware assembly
EasyPIC PRO v7a Display Selection Necto Step hardware assembly
Necto image step 9 hardware assembly
Necto image step 10 hardware assembly
Necto PreFlash Image hardware assembly

Track your results in real time

Application Output

After pressing the "FLASH" button on the left-side panel, it is necessary to open the UART terminal to display the achieved results. By clicking on the Tools icon in the right-hand panel, multiple different functions are displayed, among which is the UART Terminal. Click on the offered "UART Terminal" icon.

UART Application Output Step 1

Once the UART terminal is opened, the window takes on a new form. At the top of the tab are two buttons, one for adjusting the parameters of the UART terminal and the other for connecting the UART terminal. The tab's lower part is reserved for displaying the achieved results. Before connecting, the terminal has a Disconnected status, indicating that the terminal is not yet active. Before connecting, it is necessary to check the set parameters of the UART terminal. Click on the "OPTIONS" button.

UART Application Output Step 2

In the newly opened UART Terminal Options field, we check if the terminal settings are correct, such as the set port and the Baud rate of UART communication. If the data is not displayed properly, it is possible that the Baud rate value is not set correctly and needs to be adjusted to 115200. If all the parameters are set correctly, click on "CONFIGURE".

UART Application Output Step 3

The next step is to click on the "CONNECT" button, after which the terminal status changes from Disconnected to Connected in green, and the data is displayed in the Received data field.

UART Application Output Step 4

Software Support

Library Description

This library contains API for Clock Gen Click driver.

Key functions:

  • clockgen_set_frequency - This function sets clock divider

  • clockgen_setup_pll - This function sets pll

  • clockgen_setup_multisyinth - This function sets clock frequency on specific clock

Open Source

Code example

This example can be found in NECTO Studio. Feel free to download the code, or you can copy the code below.

/*!
 * \file 
 * \brief ClockGen Click example
 * 
 * # Description
 * Clock Gen Click represent a replacement for crystals, crystal oscillators, VCXOs, phase-locked 
 * loops (PLLs), and fanout buffers. This click features an I2C configurable clock generator 
 * based on a PLL + high resolution MultiSynth fractional divider architecture which can generate
 * any frequency up to 200 MHz with 0 ppm error. The chip on click is capable of generating 
 * synchronous or free-running non-integer related clock frequencies at each of its outputs 
 * (CLK0, CLK1, and CLK2), enabling one device to synthesize clocks for multiple clock domains in a design.
 *
 * The demo application is composed of two sections :
 * 
 * ## Application Init 
 * Configures device to default function that enables clock 0 and disables all others.
 * 
 * ## Application Task  
 * Changes 4 different frequency in span of 5 seconds.
 * 
 * 
 * \author MikroE Team
 *
 */
// ------------------------------------------------------------------- INCLUDES

#include "board.h"
#include "log.h"
#include "clockgen.h"

// ------------------------------------------------------------------ VARIABLES

static clockgen_t clockgen;
static log_t logger;

// ------------------------------------------------------ APPLICATION FUNCTIONS

void application_init ( void )
{
    log_cfg_t log_cfg;
    clockgen_cfg_t cfg;
    
    /** 
     * Logger initialization.
     * Default baud rate: 115200
     * Default log level: LOG_LEVEL_DEBUG
     * @note If USB_UART_RX and USB_UART_TX 
     * are defined as HAL_PIN_NC, you will 
     * need to define them manually for log to work. 
     * See @b LOG_MAP_USB_UART macro definition for detailed explanation.
     */
    LOG_MAP_USB_UART( log_cfg );
    log_init( &logger, &log_cfg );
    log_info( &logger, "---- Application Init ----" );

    //  Click initialization.

    clockgen_cfg_setup( &cfg );
    CLOCKGEN_MAP_MIKROBUS( cfg, MIKROBUS_1 );
    clockgen_init( &clockgen, &cfg );

    clockgen_default_cfg( &clockgen );
    
    Delay_ms( 500 );
}

void application_task ( void )
{
    clockgen_set_frequency( &clockgen, CLOCKGEN_CLOCK_0, CLOCKGEN_PLLA, 1 );
    Delay_ms( 5000 );
    clockgen_set_frequency( &clockgen, CLOCKGEN_CLOCK_0, CLOCKGEN_PLLA, 3 );
    Delay_ms( 5000 );
    clockgen_set_frequency( &clockgen, CLOCKGEN_CLOCK_0, CLOCKGEN_PLLA, 10 );
    Delay_ms( 5000 );
    clockgen_set_frequency( &clockgen, CLOCKGEN_CLOCK_0, CLOCKGEN_PLLA, 5 );
    Delay_ms( 5000 );
}

void main ( void )
{
    application_init( );

    for ( ; ; )
    {
        application_task( );
    }
}


// ------------------------------------------------------------------------ END

Additional Support

Resources