Improve data storage, speed, and reliability with CY15B108Q and STM32F103RB

Excelon-LP Click is based on the CY15B108Q, a serial ferroelectric (FRAM) module with 8Mbit density made by Infineon. It contains 1024 KB of available memory space. This memory module is manufactured using ferroelectric technology, which has many advantages over conventional technologies for manufacturing conventional EEPROM and FLASH memory modules. Ferroelectric technology is still being developed and perfected, but the main advantages have already been demonstrated. This technology exploits the properties of ferroelectric materials to retain the electric field after exposure, the same way the ferromagnetic materials retain the magnetic field. This phenomenon is employed to polarize the FRAM cells and store the information. One area that still needs improvement is the thermal instability, especially at high temperatures. When the ferroelectric material reaches the Curie temperature, its properties are degraded. Therefore, exposure to high temperatures might damage the content of the FRAM module. This is illustrated by the data retention period in the datasheet: while working at 85˚C, the data retention period is reduced to 10 years. At 65˚C, the data retention period is over 150 years. Still, combined with the endurance of 1014 read/write cycles at bus write speed, this type of memory still represents an ideal solution for applications that must do frequent writing to the non-volatile memory locations. Excelon LP click uses the SPI communication protocol, allowing fast serial clock rates. The device employs certain protection mechanisms to ensure reliable data

transactions and avoid accidental writing to the memory array. The WEL bit must be set before writing any data to the IC, which modifies registers or the array itself. This bit is cleared after or during every memory modification instruction. Therefore, every memory modification instruction must be prefixed with the Write Enable (WREN) instruction that sets this bit to 1. This mechanism ensures that only the intended write instruction will be executed. The host MCU initiates Communication with the device, which drives the chip select pin (#CS on the schematic) to a LOW logic level. This pin is routed to the mikroBUS™ CS pin. The next byte of information can be either command or data. Usually, the first byte is the instruction (command) followed by the memory address. Depending on the command sent, either the memory is written to or read from the specific memory address. The memory address on this device is 20-bit (0x000000 to 0x0FFFFF), and therefore, it is sent by 3 bytes. Several instruction codes can be sent after the CS pin is driven to a LOW logic level. These include Write Enable, Write to the memory array, Read from the memory array, Write Status Register, Read Status Register, and so on. For a full list of commands and their detailed description, please refer to the datasheet of the CY15B108Q IC. When using the write-to-array instruction, it is possible to write the whole array while keeping the CS line to a LOW logic level, as the internal address pointer will increase with each received byte of data once the end of the array is reached (address 0x0FFFFF), the internal pointer will rollover from the beginning

(0x000000). An obvious advantage over the traditional EEPROM can be observed here: on a traditional EEPROM, the memory is organized in pages, usually 256 bytes long, which allows buffering of the data because of the inherently slow write operation. The FRAM memory does not use pages because the memory is written faster than the SPI bus can deliver new information (the data is written at bus speed). Therefore, no buffering is required, and the whole array can be sequentially written. The CY15B108Q includes the option to write-protect specific parts or the whole memory array. The write protection mechanism consists of two bits in the Status Register (BP0, BP1). The Write Status Register instruction can set or reset these bits. BP0 and BP1 bits control the write-protect status of the memory array (from one-quarter to full memory array protection). These bits are non-volatile, and their state is retained between the power cycles. The #WP pin is used to lock the Status Register. When this pin is driven to a LOW level, no further modifications to the Status register are possible, and the instructions used to change bits in this register (Write Enable and Write Status Register) are completely ignored. Driving this pin to a LOW state effectively acts as the hardware memory write-protect lock mechanism. The WPEN bit of the status register can completely turn off this pin: if the WPEN bit is cleared (0), this pin will not affect the CY15B108Q IC. The #WP pin is routed to the mikroBUS™ PWM pin.

Nucleo-64 with STM32F103RB MCU offers a cost-effective and adaptable platform for developers to explore new ideas and prototype their designs. This board harnesses the versatility of the STM32 microcontroller, enabling users to select the optimal balance of performance and power consumption for their projects. It accommodates the STM32 microcontroller in the LQFP64 package and includes essential components such as a user LED, which doubles as an ARDUINO® signal, alongside user and reset push-buttons, and a 32.768kHz crystal oscillator for precise timing operations. Designed with expansion and flexibility in mind, the Nucleo-64 board features an ARDUINO® Uno V3 expansion connector and ST morpho extension pin

headers, granting complete access to the STM32's I/Os for comprehensive project integration. Power supply options are adaptable, supporting ST-LINK USB VBUS or external power sources, ensuring adaptability in various development environments. The board also has an on-board ST-LINK debugger/programmer with USB re-enumeration capability, simplifying the programming and debugging process. Moreover, the board is designed to simplify advanced development with its external SMPS for efficient Vcore logic supply, support for USB Device full speed or USB SNK/UFP full speed, and built-in cryptographic features, enhancing both the power efficiency and security of projects. Additional connectivity is

provided through dedicated connectors for external SMPS experimentation, a USB connector for the ST-LINK, and a MIPI® debug connector, expanding the possibilities for hardware interfacing and experimentation. Developers will find extensive support through comprehensive free software libraries and examples, courtesy of the STM32Cube MCU Package. This, combined with compatibility with a wide array of Integrated Development Environments (IDEs), including IAR Embedded Workbench®, MDK-ARM, and STM32CubeIDE, ensures a smooth and efficient development experience, allowing users to fully leverage the capabilities of the Nucleo-64 board in their projects.