Secure data integrity with CY15B104Q and ATmega328

FRAM 2 Click is based on the CY15B104Q, a 4 Mbit serial ferroelectric (FRAM) module from Infineon. It contains 4,194,304 bits of memory, organized in 524,288 byes. This means that the storage area contains 512 KB of address space. This memory IC is manufactured using ferroelectric technology, which has many advantages over the conventional technologies used for manufacturing EEPROM and FLASH memory modules. Ferroelectric technology is still being developed and perfected, but the advantages have already been demonstrated. This technology exploits the properties of ferroelectric materials to retain the electric field after exposure, the same way the ferromagnetic materials retain their magnetic field. This phenomenon is employed to polarize the FRAM cells and store the information. One area that still needs improvement is the thermal instability, especially at high temperatures. When the ferroelectric material reaches the Curie temperature, its properties are degraded. Therefore, the high temperature might damage the content of the FRAM module. This is illustrated by the data retention period: while working at 85˚C, the data retention period is reduced to 10 years. At 65˚C, the data retention period stretches to over 150 years. Still, combined with the endurance of 1014 read/write cycles at bus write speed, this type of memory still represents an ideal solution for applications with frequent writing to non-volatile memory locations. This Click board™ uses the SPI communication protocol, allowing fast serial clock rates. The device employs certain protection mechanisms to ensure reliable data transactions and avoid accidental writing to the memory array. The WEL bit must be set before

writing any data to the IC, which modifies registers or the array itself. This bit is cleared after or during every memory modification instruction. Therefore, every memory modification instruction must be prefixed with the Write Enable (WREN) instruction that sets this bit to 1. This mechanism ensures that only the intended write instruction will be executed. The host MCU initiates Communication with the device, which drives the chip select pin (#CS on the schematic) to a LOW logic level. This pin is routed to the mikroBUS™ CS pin. The next byte of information can be either command or data. Usually, the first byte is the instruction (command) followed by the memory address. Depending on the command sent, either the memory is written to or read from the specific memory address. The memory address on this device is 19-bit (0x00000 to 0x7FFFF), and therefore, it is sent by 3 bytes. Several instruction codes can be sent after the CS pin is driven to a LOW logic level. These include Write Enable, Write to the memory array, Read from the memory array, Write Status Register, Read Status Register, and so on. For a full list of commands and their detailed description, please refer to the datasheet of the CY15B104Q IC. When using the write-to-array instruction, it is possible to write the whole array while keeping the CS line to a LOW logic level, as the internal address pointer will increase with each received byte of data. Once the end of the array is reached (address 0x7FFFF), the internal pointer will roll over from the beginning (0x00000). An obvious advantage over the traditional EEPROM can be observed here: on a traditional EEPROM, the memory is organized in pages, usually 256 bytes long, which allows

buffering of the data because of the inherently slow write operation. The FRAM memory does not use pages because the memory is written faster than the SPI bus can deliver new information (the data is written at bus speed). Therefore, no buffering is required, and the whole array can be sequentially written. The CY15B104Q includes the write protection of the specific parts or the whole memory array. The write protection consists of two bits in the Status Register (B0, B1). The Write Status Register instruction can set or reset these bits. B0 and B1 bits control the write-protect status of the memory array (from one-quarter to full memory array protection). These bits are non-volatile, and their state is retained between the power cycles. The #WP pin is used to lock the Status Register. When this pin is driven to a LOW level, no further modifications to the Status register are possible, and the instructions used to change bits in this register (Write Enable and Write Status Register) are completely ignored. Driving this pin to a LOW state effectively acts as the hardware memory write-protect lock mechanism. The WPEN bit of the status register can completely turn off this pin: if the WPEN bit is cleared (0), this pin will not affect the CY15B104Q IC. The #WP pin is routed to the mikroBUS™ RST pin and labeled as WP. The FRAM 2 click allows hold of the communication in progress. If the #HOLD pin is driven to a LOW logic level on the LOW pulse of the serial clock signal (SCK), the communication will be paused but not aborted. Driving this pin to a HIGH logic level will resume the data transfer. This pin is routed to the mikroBUS™ PWM pin, labeled as HLD.

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